Generally, a super junction structure has been widely used to improve a trade-off relation between forward characteristics and reverse characteristics related to a breakdown voltage in a power semiconductor device.
According to the prior art, pillars and gate structures in the super junction MOSFET have the same layout. Examples of the layout include a linear array, a square array, a hexagonal array, and the like.
An on-resistance Rsp increases in proportion to an area occupied by the pillars in an active region. An input capacitance also increases in proportion to an area occupied by the gate structure. The area of the pillars decreases in an order of the linear array, the square array, and the hexagonal array. The area of the gate structure increases in an order of the linear array, the square array, and the hexagonal array.
Therefore, when the layouts of the pillars and the gate structure are linear, the on-resistance increases because of a relatively large area of the pillars, but the input capacitance decreases due to a relatively small area of the gate structure.
Meanwhile, when the layouts of the pillars and the gate structure are hexagonal, the on-resistance decreases due to a relatively small area of the pillars, but the gate capacitance increases due to a relatively large area of the gate structure.
Therefore, there is still a need for a layout of the pillars and the gate structure that can reduce the on-resistance as well as the input capacitance simultaneously.